REPOST: Re: High Bandwidth Mixing Cipher Chips

tomstdenis_at_gmail.com
Date: 10/28/05 

Date: 28 Oct 2005 13:13:08 -0700

Jan Panteltje wrote:
> FPGA are not cheap. I already pointed out that logic units and
> gates is divergent in synthesis.
> (You will probably run out of logic units, while there are still free gates
> in these...).
> It all depends Tom, the cost of the FPGA in these small to medium scale
> projects (else it would be ASIC) is often hardly a fraction of
> what a customer has to pay for design, other overhead, hardware, documentation,
> etc. etc.
> So it makes little sense to spend 3 month hard work resulting in a 10%
> savings in gates..... Time is expensive.

Ok, granted but bringing this full circle ...

There are more efficient designs than what Terry is proposing. That's
my point.

It's like the state of art in ECC is "the way it is". Sure it would be
nice if you could do 200 million ECC signatures a second but that isn't
the case. But given that it doesn't make sense to invent slow methods
of ECC just becuase you want your ideas expressed.

His design is not secure. That's trivial to show.

His design is also not practical as the 37k registers he requires is
quite a bit [and I'm not even counting control logic or the latin
squares at that point].

There ARE smaller and equally fast block ciphers out there. Where he
pulled 450Mhz from is beyond me [nor does he mention in what technology
that is ... FPGA? 0.18um? 0.13um? slow speed or? ...].

And really if you're incapable of implementing a fast block cipher like
AES you should just license a design from one of the many dozens of
companies that provide AES IP.

Tom

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From: tomstdenis@gmail.com
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Subject: Cancel "Re: High Bandwidth Mixing Cipher Chips"
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Date: Fri, 28 Oct 2005 18:46:17 GMT
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  • REPOST: Re: High Bandwidth Mixing Cipher Chips
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