Re: High Bandwidth Mixing Cipher Chips

panteltje_at_yahoo.com
Date: 10/28/05 

Date: 28 Oct 2005 12:02:53 -0700

>
> So I repeat that the design is not well suited for hardware
> implementation.
>
> Tom
Have you ever taken a cypher, written it in a HDL, programmed a FPGA
and had it working?
yes [ ]
no [ ]
dunno [ ]

Relevant Pages

  • REPOST: Re: High Bandwidth Mixing Cipher Chips
    ... > So I repeat that the design is not well suited for hardware ... Have you ever taken a cypher, written it in a HDL, programmed a FPGA ... Subject: Cancel "Re: High Bandwidth Mixing Cipher Chips" ...
    (sci.crypt)
  • Re: Security and EOL issues
    ... OS software resources are designed that reserved ram and disk space among other resources, to reflect what current hardware size is available. ... (There was a security patch a few years ago that could not be applied to NT4 as it required more resources then NT4 could provide. ... Installing air bags requires that the automobile manufacturer design, test, ... Computer Emergency Response Teams, and Digital Investigations. ...
    (Security-Basics)
  • Re: Now THIS is Meshuga - Do NOT bring your IPad to Israel
    ... can't write applications for the iPad without having one. ... When you write a novel, you would prepare and outline, design how ... wrote the specs for the next product while the developers where still ... So as I said before, you don't need the hardware to write code, you ...
    (soc.culture.jewish.moderated)
  • Staff HW Engineer ~ Lead Us to ATCA & Beyond in Your End-to-End Board-Level HW Desig
    ... The senior level hardware engineer looking for the product realization ... and true ownership that comes with full end-to-end board-level hardware ... help us retain dominance in the design of high performance switching ...
    (comp.arch.embedded)
  • Re: 10khz DBSK decoder
    ... In an AVR, you may want to come closer to the 'hardwareish' thing: run the whole thing as a Costas loop or as a signal-square-and-PLL, and do integrate-and-dump. ... In retrospect, the ISR should have just taken ADC samples and shoved them into a queue, then set a flag. ... But I had never seen that design pattern, so it just ran with that big bloated ISR... ... You'll get more consistent timing if you can trigger your ADC from hardware and interrupt on the end of conversion pulse. ...
    (comp.dsp)