Re: High Bandwidth Mixing Cipher Chips
Date: 10/28/05

Date: 28 Oct 2005 11:00:15 -0700

Jan Panteltje wrote:
> hey hey. not so agressive. I have no shares in either of these companies.
> But I have some practical experience designing with FPGA.
> And imnplementing some crypto in it.
> You will NEED a lot of space (gates) if you use FPGA.
> In fact the 'gates' (not referring to Billy from MS) is something tricky.
> Think logic blocks, although one such block may hold several gates, that
> does not mean synthesisis can use all of these randomly.
> You will not that on that Xilinx site (the link I showed) in the Virtex
> they do not even mention 'gate count' anymore.
> And really, PC is not the whole world, embedded is.

This conversation is seriously derailed.

Me: The design is not efficient, it's too big.
You: They make large FPGAs
Me: So what? They also make smaller FPGAs
You: So what? They make large FPGAs

Congrats, I know they make large FPGAs. And in case you need further
submarining ...

If you take a space efficient cipher it leaves you more room in the
FPGA for PDU work. It's hard to argue that "oh it's ok to use lots of
gates, there are always more" and not get laughed at.

And yes, you're right that gate != transistor but that said there are
only so many CLBs in an FPGA. The more you waste on your cipher the
fewer you have for anything else.

So I repeat that the design is not well suited for hardware