Re: High Bandwidth Mixing Cipher Chips

From: Jan Panteltje (pNaonStpealmtje_at_yahoo.com)
Date: 10/28/05 

Date: Fri, 28 Oct 2005 15:11:22 GMT

On a sunny day (28 Oct 2005 07:42:40 -0700) it happened tomstdenis@gmail.com
wrote in <1130510560.930336.156130@g47g2000cwa.googlegroups.com>:

>You missed my point. Let me give you a real life example. Ever use a
>wifi access point? Think the crypto is done in software?
No, bit could be, really dunno, I avoid wireless for ANY confidential data.

>In these cases they most likely use an ASIC but a lower level entry
>into the market may choose to use an FPGA. In this case you still do a
>lot of work in the processor just offload the crypto to the FPGA.
All depends, if the processor can be in the FPGA too, cost, board space,
yes ASIC is very expensive, no 'updates' possible, this flexibility
can be very important, also for big companies.

>Why would you want to pay for a 1.5M gate FPGA when you can cram AES
>into [say] 30K gates? The 30K part will be much cheaper and get you
>AES much faster than a MIPS or ARM processor can deliver.
Well, my personal experience with crypto in FPGA is that I ran out of the
200k gates Spartan space first project I tried ;-)
It looks a lot, but once you synthesize the design it is not..

>We're not talking PCs here. I mean my AMDx2 box can crank out over a
>gigabit of AES [inside the cache at least] and I can fully saturate my
>IDE channels and then some with AES traffic.
Yes AMD is cool.... but think for example an optical link with real
time encryption / decryption FPGA (or ASIC OK) is a nice way to go and make
that speed.
There may be no PC in between even, could go directly to a VGA monitor
for example...
There is a trend... mpeg(4) etc encoding engine in FPGA, single chip,
low cost high volume.... All logic in one chip... look what Altera is doing
with the FPGA and video these days..
Somebody will use FPGA perhaps to decode HDMI... ;-)
Very high speed differential, looks interesting... Then anybody can copy
the HDL.... I have been scribbling diagrams some time ago.
There is a lot of choice ATM as far as these chips are concerned.
And for small to medium size series designing ASIC is out of the question.

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