Re: High Bandwidth Mixing Cipher Chips

From: Jan Panteltje (pNaonStpealmtje_at_yahoo.com)
Date: 10/28/05 

Date: Fri, 28 Oct 2005 14:31:15 GMT

On a sunny day (28 Oct 2005 07:04:22 -0700) it happened tomstdenis@gmail.com
wrote in <1130508262.299456.270910@g47g2000cwa.googlegroups.com>:

>One low cost development tactic is to bundle an FPGA with an embedded
>processor. Now do you want to use 1.6M gate parts or the smaller
>30K-50K parts?
>
>This is analogous to saying "we can always throw more cycles at it".
>
>Tom
I am not 100% sure I understand what you are trying to say.
Some things are easier to program in normal sequential code, and, depending
on the application, you may or may not need a lot of 'free configurable
logic'.
In those cases where the FPGA is not non-volatile (like for example the Actel
FLASH ones), you will need an external ROM (or something for configuration
data) and perhaps a processor ./ microcontroller (FLASH ) anyways, so it
is the hardware designers option to select the best / cheapest configuration.
Ain't no telling really, you can have an FPGA card in the PC....

All I was pointing out is that the number of gates is quite high these days,
and will only increase.
That allows one to 'unroll' any loops in the crypto hardware.. good stuff!
Do everything in one clock!
And the clock speeds go up too.
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