Re: High Bandwidth Mixing Cipher Chips

From: Jan Panteltje (pNaonStpealmtje_at_yahoo.com)
Date: 10/28/05 

Date: Fri, 28 Oct 2005 12:55:14 GMT

On a sunny day (28 Oct 2005 04:47:29 -0700) it happened tomstdenis@gmail.com
wrote in <1130500049.913929.296290@f14g2000cwb.googlegroups.com>:

>
>tomstde...@gmail.com wrote:
>> 3. 512-byte block at 450Mhz? You're kidding right? That's 4096-bits
>> of registers at the very least. Then you want to go through 9 layers
>> of 2-dimensional sboxes in 1/450Mhz of a second? This will be a VERY
>> BIG circuit.
>
>I mis-read that... it's even worse. You described a pipeline ... 9
>levels deep... that's 9*4096 bits of registers at a minimum. A
>register is basically a flipflop [e.g. ~8 gates or ~6 transistors]
>that's 300K gates just for the registers. Now you have 512*9 latin
>squares ... You're probably looking at north of 400-500K gates [e.g.
>not suitable for an FPGA] and in the case of an ASIC it's probably
>larger than the average ECC core :-)
Tom, you seem a bit rusty on FPGA size...
Even for a modest Spartan equivalent of 1 600 000 gates is in the shops:
http://www.xilinx.com/products/silicon_solutions/fpgas/product_tables.htm#Spartan3E

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