Re: Ciphers versus S/W &H/W
From: Tom St Denis (tomstdenis_at_yahoo.com)
Date: 09/16/03
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Date: 16 Sep 2003 03:28:33 -0700
"Panu Ha:ma:la:inen" <panu.hamalainen@NOSPAM.tut.fi.invalid> wrote in message news:<bk3ok7$hhq$1@news.cc.tut.fi>...
> The main reason why dedicated HW is faster than SW is that in HW the execution
> is parallel. For example, if an algortihm operates on 64-bit data, in SW it
> usually has to be divided into two 32-bit parts which are processed seperately
> and serially. In HW the 64-bit data can be operated as a whole. Modular
> exponentiation probably benefits the most of this property.
Yes part of that is true. The big reason why HW can always win is
that a processor to run SW is in fact HW [no duh :-)]. So for example
if you had to add two 32-bit variables you could just make a 32-bit
adder. In SW you have to
make an ADD opcode, decode it, issue it, run it, etc. For the most
part efficient processors will break up this task and it will will run
reasonably
fast [1 cycle on an Athlon which at 2Ghz is wicked fast]. But you
always have the processor in the way.
However, part of the reason why HW designs often seem "inferior" is
cost. Designing a true hardware design [and not an FPGA] cost a
hella-lot of money. You need a team of designers who want 80K/year,
then you need the tools to design, simulate and such a core. Then
let's not forget the good ol' renting time at one of IBMs foundries to
actually make the die, etc....
FGPAs can be faster than SW for certain tasks but not always due to
resource restraints. It really depends solely on the algorithm.
I don't know where you got your modular exponentiation idea but a
decent modern processor would whoop an FPGAs ass any day at such a
task. Let me know when you find an FPGA that has three ALUs, 384KB of
cache, 6-cycle [@2Ghz] full multiplier and then we're talking :-)
> HW is always at least as fast as SW since SW is always run on HW.
Essentially yes except HW [at least in crypto terms] is almost always
FPGA designs.
Tom
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