Re: More LTC timings...

From: Brian Gladman (fake_at_nowhere.org)
Date: 06/17/03


Date: Tue, 17 Jun 2003 19:34:45 +0100


"Mok-Kong Shen" <mok-kong.shen@t-online.de> wrote in message
news:3EEF5256.FCD32498@t-online.de...
>
>
> Brian Gladman wrote:
> >
> > "Tom St Denis" <tomstdenis@iahu.ca> wrote:
> .......
> [snip]
>
> > That is doubtful. My results 3 years ago for Twofish in C as described
> > here:
> >
> > http://fp.gladman.plus.com/cryptography_technology/aesr2/index.htm
> >
> > give 370 cycles per block and 8500 cycles for key setup.
>
> I have a question of ignorance: I remember to have read
> a book on assembler, in which it is listed for each
> instruction the number of cycles for diverse types of
> chips, i.e. the same instruction may have different
> cycles on different machines. Now, if one measures
> the total time of a program on a machine and deduce
> from the MHz of the hardware the total number of cycles
> involved, would that figure remain the same on a
> machine having a different type of chip? (The Intel
> family has a number of members.) Or is the above
> stemming from a sheer misunderstanding (or wrong
> memory) of mine? Thanks.

The number of cycles for an algorithm used to be a fairly good measure of
the performance of source code but it is getting much less reliable now and
is becoming more a test of how good compiler writers (actually back end
writers) are at understanding and exploiting modern machines which have very
sophisticated mechanisms for speeding up code execution.

Moreover, different machines in the same family are often radically
different in terms of performance. For example an MMX version of AES on the
P3 runs in 270 cycles but on the P4 is takes 420 cycles. And Tom's figures
show that Athlons and P4's give very different results.

     Brian Gladman