Re: weird scans from port 80

From: Silviu Minut (silviu@orion.attbi.com)
Date: 01/20/03


From: Silviu Minut <silviu@orion.attbi.com>
Date: Mon, 20 Jan 2003 11:23:29 -0500

On Mon, 20 Jan 2003 08:33:06 -0500, Bill K. wrote:

> In article <3E2ACF08.D4978104@daimi.au.dk>, "Kasper Dupont"
> <kasperd@daimi.au.dk> wrote:
>
>> From RFC 793 page 36:
>>
>> As a general rule, reset (RST) must be sent whenever a segment
>> arrives which apparently is not intended for the current connection.
>
> The next sentence reads: "A reset must not be sent if it is not clear
> that this is the case."
>
> Why did you snip it?
>
> Sorry for butting in.

This is really funny, it made my day. This deems this discussion useless,
doesn't it? Except for the articles addressing directly my unusual logs.



Relevant Pages

  • Re: weird scans from port 80
    ... reset (RST) must be sent whenever a segment ... > arrives which apparently is not intended for the current connection. ...
    (comp.os.linux.security)
  • Re: converting verilog to vhdl
    ... Verilog code to VHDL. ... reset after the register. ... The only difference in behavior would be if rst is high for ... (in which case the original circuit output would be 0 while rst, ...
    (comp.arch.fpga)
  • Re: converting verilog to vhdl
    ... Verilog code to VHDL. ... reset after the register. ... The only difference in behavior would be if rst is high for ... (in which case the original circuit output would be 0 while rst, ...
    (comp.arch.fpga)
  • Re: converting verilog to vhdl
    ... Verilog code to VHDL. ... reset after the register. ... The only difference in behavior would be if rst is high for ... (in which case the original circuit output would be 0 while rst, ...
    (comp.arch.fpga)
  • Re: Infer RS FlipFlop
    ... i.e. clocked device with separate async set and reset like a 7474. ... infers, as long as it acts like an RS flip-flop. ... always @ (set or rst) ...
    (comp.lang.verilog)