Re: cvs commit: src/sys/amd64/amd64 mp_machdep.c src/sys/i386/i386 mp_machdep.c


Am 24.04.2006 um 23:17 schrieb Colin Percival:

cperciva 2006-04-24 21:17:02 UTC

FreeBSD src repository

Modified files:
sys/amd64/amd64 mp_machdep.c
sys/i386/i386 mp_machdep.c
Log:
Adjust dangerous-shared-cache-detection logic from "all shared data
caches are dangerous" to "a shared L1 data cache is dangerous". This
is a compromise between paranoia and performance: Unlike the L1 cache,
nobody has publicly demonstrated a cryptographic side channel which
exploits the L2 cache -- this is harder due to the larger size, lower
bandwidth, and greater associativity -- and prohibiting shared L2
caches turns Intel Core Duo processors into Intel Core Solo processors.

As before, the 'machdep.hyperthreading_allowed' sysctl will allow even
the L1 data cache to be shared.

I do not pretend to understand the background, but from your description it sounds like performance on Core Duo machines will be bad unless this change is made, or the potentially dangerous sysctl is active. If that is indeed the case, will this change make it into 6.1?


Thanks,
Stefan

--
Stefan Bethke <stb@xxxxxxxxxx> Fon +49 170 346 0140


_______________________________________________
freebsd-security@xxxxxxxxxxx mailing list
http://lists.freebsd.org/mailman/listinfo/freebsd-security
To unsubscribe, send any mail to "freebsd-security-unsubscribe@xxxxxxxxxxx"

Relevant Pages

  • [PATCH 23/43] MN10300: Cache: Implement SMP global cache flushing
    ... Implement SMP global cache flushing for MN10300. ... * Flush the data cache on all CPUs. ... * Flush and invalidate the data cache on all CPUs. ...
    (Linux-Kernel)
  • Re: mips per watt - ARM vs. X86
    ... It is possible to implement a data cache with an access-width spanning ... But also provide unit stride instructions. ...
    (comp.arch)
  • Cache trouble in XPS
    ... When using data cache in xilinx platform studio, ... BRAM, but when enabled for the DDR memory, faulty data is read from memory. ...
    (comp.arch.fpga)
  • Cache trouble in Xilinx XPS
    ... When using data cache in xilinx platform studio, ... BRAM, but when enabled for the DDR memory, faulty data is read from memory. ...
    (comp.arch.fpga)
  • RE: fast deep-copying of instances
    ... > i have a data cache which sits between a slow database and ... > it's used to cache data retrieved from the database. ... The latter is called to implement the deep copy operation; ...
    (comp.lang.python)